IC design and reliability: Failure rate and the FIT

The failure rate for ICs is defined by: (Number of devices failed/Total number of devices tested)(1/time). The units can be stated as failures per device hour. This is an important parameter and has to be considered as early as possible in the design of the device. A unit called a FIT can also be defined. In this case a FIT = one failure per 1 billion device hours of operation. A FIT can be used to evaluate devices and distributions. The simplest model of failure is given by the parameter called the mean time to failure or MTTF. MTTF = 1/KF. Here KF is simply the failure rate per unit time. This is used in the exponential model which is very popular. The exponential model is simply expressed as: Fail(t) = 1.0 – exp(-KFt). This model is easy to use and calculate and can be used to assess the design of the device based on a failure rate model. Data is usually available from foundries for the use of this model. Please visit our website at http://www.signalpro.biz for more ASIC and module design and manufacturing information. Please contact SPG for detailed information on more extended types of failure expressions and their use in the design of devices. i.e how these failure parameters mesh with design parameters that allow the design to be more robust in terms of MTTF or failure rate.

We design and deliver analog and RF/wireless ASICs and modules using state of the art semiconductor, PCB and assembly technologies. Please contact us at spg@signalpro.biz for a quote and a proposal.

IC design and reliability issues

Reliability is a key issue with complex ASICs. Reliability data is important to the cost and long term performance assessment of the device and indirectly of the entire module, and ultimately to the system itself. The operating conditions that affect reliability are: (1) Temperature (2) Humidity (3) Temperature cycling (4) Voltage stresses (5) Current stresses. These stresses if applied with sufficient magnitude, will cause rapid deterioration and ultimate failure of the device. So it is only logical to use these stresses to evaluate reliability of the device. JEDEC stress testing standards are one way to come up with set of approaches to assess the reliability of the device. The website is http://jedec.org.

We design and deliver analog and RF/wireless ASICs and modules using state of the art semiconductor, PCB and assembly technologies. Please contact us at spg@signalpro.biz for a quote and a proposal.

IC design for mini(TM)ASICs and macro(TM)ASICs.

We have divided the ASIC types that we develop into two categories. These are the miniASIC and the macroASIC. This nomenclature applies to the functionality, size, complexity, cost and risk of the device. A miniASIC is a device with very few elements on it. It is small in size ( remember size differentiation; 50 mils on a side is small, 100 mils on a side is medium and 250 mils+ on a side is large for analog, RF, wireless or mixed signal ASICs). Examples are: 2 power/high voltage MOSFETs, a closely matched high frequency differential stage, multiple bipolars or MOSFETs on a chip (used largely for bread-boarding and proof of concept sometimes. Although these can be valuable adjuncts to a board design in production as well.) A low logic gate device, more logic gates than a CD4000 series device perhaps, but less than a large digital design ( 5k gates+). Matched resistors, capacitors, inductors and interconnect on a chip. A macroASIC on the other hand lies at the other end of the spectrum. It is a larger device,(definition above), it is more complex and costs more. In our experience both types come in handy when developing systems. The miniASIC can be used as part of glue circuitry ( when the exact device you need is not available of the shelf and it has to be cheap). The macroASIC is the device of choice when you want to sweep many discrete components on to a piece of silicon ( or GaAS, SiGe, GAN, etc)to provide enhanced performance, reduction in cost, safety of R&D, increased reliability and manufacturability, testability, and so on. Signal Processing Group Inc., provides both types of devices. The only drawback is of course that you cannot just go out and buy something quickly off the shelf. Lead times for these ASICS is of the order of 2 to 10 weeks. However, if the planning takes this into account then mini and maro ASICs become a sound choice. Please visit our website at http://www.signalpro.biz for more info.

We design and deliver analog and RF/wireless ASICs and modules using state of the art semiconductor, PCB and assembly technologies. Please contact us at spg@signalpro.biz for a quote and a proposal.

Image reject mixer: Description of operation

Image reject mixers are interesting circuits used in RF/wireless receivers to avoid the problems associated with the image frequency. ( To read about the image frequency please search for “image frequency” in this blog). A recent white paper from Signal Processing Group Inc, examines the operation of the image reject mixer and provides a fairly detailed explanation of the operation for interested readers. Please visit our website at http://www.signalpro.biz and click on the free reports link for a detailed description of the image reject mixer.

We design and deliver analog and RF/wireless ASICs and modules using state of the art semiconductor, PCB and assembly technologies. Please contact us at spg@signalpro.biz for a quote and a proposal.

Injection locking in transmitter chips

An interesting titbit of knowledge about direct conversion transmitters is the phenomenon of injection locking. If the transmitter is such that right after the modulation the signal goes to the driver/PA ( i.e there is no up-conversion or filtering of any kind between the PA and the modulator and its associated LO, then feedback from the output can cause ( in a number of cases) the LO frequency to shift and lock to another harmonic of a feedback signal. A number of techniques to alleviate this have been investigated because the direct conversion technique is considered by some to be simple and easy to handle ( keep chip size small). For more information or articles visit our website at http://www.signalpro.biz.

We design and deliver analog and RF/wireless ASICs and modules using state of the art semiconductor, PCB and assembly technologies. Please contact us at spg@signalpro.biz for a quote and a proposal.

Dot rule for magnetically coupled circuits ( baluns and transformers)

In a magnetically coupled circuit like a balun or a transformer the phasing of currents and voltages is commonly indicated by the dot rule. Place a dot at either end of the primary. Drive this end positive ( for example). Measure the voltage at the secondary ends. The end of the secondary which is also positive ( or generally in phase ) with the primary end is also indicated by a dot. The other end of the secondary will be 180 degrees out of phase. Current flowing into the dotted terminal at the primary end will cause the current to flow out of the dotted end of the secondary and vice versa. Visit our website for more information and articles of interest at http://www.signalpro.biz.

We design and deliver analog and RF/wireless ASICs and modules using state of the art semiconductor, PCB and assembly technologies. Please contact us at spg@signalpro.biz for a quote and a proposal.

VSWR control on chip

High levels of mismatch, for example in a transmitter or any output power device, can sometimes cause catastrophic failure of the device and its associated subsystem. Depending on the application this can be a severe problem. An interesting approach to prevent or control these types of failures is the use of an on chip integrated power detector. The power detector is used to estimate reflected power and if the VSWR (matching) gets really bad ( due to aging, component failure or other such causes) the power detector either signals a problem before it reaches irreversible levels, or executes automatic control of VSWR. Please visit our website at http://www.signalpro.biz for other interesting articles or just information.

High voltage IC design considerations

High voltage IC design is, in our opinion, an art. In terms of the implementation of the functions, simulations and layout it is a taxing endeavor. A number of fabrication vendors who offer high voltage technology try to make it as easy as they can, sometimes by providing some IP. In spite of this there are number of issues and challenges that come up, which the designer only learns through experience. When you are designing at voltages in the range of 500V to 700V and at high currents as well, it becomes a real challenge. It helps if the designer understands some of the parameters of the high voltage device, related to its operation. A white paper on this subject is available in the Signal Processing Group Inc., website located at http://www.signalpro.biz in the engineer’s corner. An old adage says ” when you are working with high voltage and specially on the bench, keep your left hand in your pocket!”

The 2-s complement number and DSP

More and more DSP ( digital signal processing) techniques are being used in most complex circuit designs including IC design. In general dsp requires the use of binary numbers. After all dsp is akin to a set of computations yielding a result which may or may not be converted into an analog signal. Both ways. At the input using an A/D and at the output using a D/A. In fact this is the way many recent designs in wireless are being implemented. The number system most often used is the 2-s complement number system. To refresh our memories, a 2-s complement number is formed by taking the binary representation of a decimal number, inverting the bits and then adding a “1” to it. This generates the 2-s complement. A wealth of articles exist on this in the literature and the web. The nice thing about the 2-s complement number is that addition and subtraction become very easy. An example is a dual modulus frequency divider. In this circuit we have two counters that start with a loaded number, an initial seed, and then this number is counted down. When the loaded number goes to zero a reset occurs. This is almost the very basic operation required in a dual modulus frequency divider. Note how easy the countdown becomes when implemented with 2-s complement numbers. Have the initial storage in a set of FFs, at each clock invert the contents of the FFs, use a simple adder, add 1 and at the falling edge of the clock recapture the results back into the storage FFs. Each time the clock occurs the FFs count down by ‘1’. Please visit the Signal Processing Group Inc., website located at http:/www.signalpro.biz for more information on our unique services, technology and technical articles. Contact us on this or other blog posts or articles as needed.

IC Design primitive components available in typical semiconductor processes

When an engineer is in the process of designing a board level product, he or she instinctively starts a search for off the shelf components that are required to implement the architecture that the engineer has chosen to satisfy the requirements of the product. Yet in some cases a particular function in the architecture cannot be realized using an off – the – shelf component. At this point the engineer may decide that he/she needs a custom part, sometimes an ASIC. The question is what kinds of typical primitive devices can a semiconductor process provide so that the required ASIC can be implemented. A reasonable list of such components is given in http://www.signalpro.biz/asictools.html for the interested reader. Please also visit http://www.signalpro.biz for more information.