Now and then we come up against expressions in the design of circuits and systems that involve the use of complex numbers under the radical sign. When this happens it turns out that the whole technique is quite complicated and may involve De Moivre’s theorem and polar form of complex numbers. Other techniques can be even more involved. Best of luck to the modelers who may be using these techniques. We found them at least as interesting as Bessels functions!
Looking at the issue of the IEEE Journal of Solid State Circuits, after the 2012 Custom IC conference, with a critical eye for analog and RF content, the following interesting articles were found. A 3W class-D ampliﬁer with improved linearity was described that reduces external ﬁltering required for EMI protection by controlling the slew rate of the driver ampliﬁer and digital modulation to spread the PWM common mode signal to place a null at the victim channel. The 110 nm CMOS design achieves SNR of 95 dB at 85% efficiency. A second article describes a 2.3 mW 10-bit 170 MS/s ADC in 65 nm CMOS using a two-step binary-search assisted time-interleaved SAR architecture. The third article , presents a continuous-time sigma-delta ADC with a switched-capacitor return-to-zero DAC that helps to reduce sensitivity to clock jitter and improves linearity. The prototype ADC was designed in a 180 nm process. It achieves an SNDR of 82.3 dB for a 2 MHz bandwidth while consuming 16.5 mW and reduces clock jitter sensitivity by 28 dB. An interesting article describes comprehensive design considerations for interleaved ADCs and proposes a background timing mismatch calibration technique to reduce the image to 75 dB for input frequencies more than 500 MHz. Another article presents a 40 nm 2.1 GS/s 2x time-interleaved pipeline ADC tthat uses a digital MDAC equalization techniques using FIR ﬁlters. The 12-bit design achieves SNDR of 52 dB while consuming 240 mW. In terms of topics in RF design some interesting articles described various RF techniques such as: A digital PLL that uses a coarse/ﬁne TDC. The ﬁne TDC is implemented using stochastic techniques to achieve an overall TDC resolution of 4 ps. The concept is demonstrated in a 130 nm 1.99–2.5 GHz PLL with 213 fs rms integrated jitter. The next paper in this series describes dynamic latches, where the regenerative cross-coupled pair is removed for maximum speed, demonstrated in prototypes of divide-by-4 circuits in 32 nm CMOS operated between 14 GHz and 70 GHz. A switched-triple-shielded transformer technique to realize a wideband CMOS VCO that can tune from 57.5 GHz to 90.1 GHz was also presented. An interesting paper provided reviews of techniques for improved harmonic reject mixers using clock gating that allow better than 52 dB rejection for 3rd/5th/7th LO harmonics without any calibration. This should be of interest to front end designers. There were papers on wireline topics as well. A paper presented a reference-less CDR for SONET transceivers that uses an algorithmic frequency acquisition without using a training sequence. The concept was demonstrated on a 65 nm transceiver that achieves 400s acquisition time and a jitter tolerance of 0.5 UI for 10 mVppd( differential) input sensitivity. Another paper on the wireline topics describes a 20 mW 6b 1.6 GS/s ADC with embedded partial equalization using a 1-tap DFE for serial receivers. The prototype receiver is demonstrated at 1.6 GS/s over 46-inch FR4 link with 14 dB loss while achieving a 0.2 UI timing margin. The next paper presented a 10 Gb/s 2-tap reconﬁgurable pre-emphasis transmitter that consumes 10 mW in a 65 nm LP CMOS. Power management was not ignored and papers described advances in power management techniques especially for SoC applications. An interesting paper for an adaptive all-digital ripple mitigation technique for fully integrated capacitive DC-DC converters was presented. Coarse ripple control was achieved by varying the size of the bucket capacitance, and ﬁne control by time modulation of the charge/discharge charge transfer capacitors. The 130 nm design presented achieved 3x ripple reduction, 70% efficiency, and 24.5 mW/mm maximum power density. A power management unit was presented with a reconﬁgurable switched-capacitor converter in 65 nm CMOS to reduce the energy cost with sleep-to-active and active-to-sleep transitions by 64%. This energy reduction comes at small area overhead (lower than 1%) and no penalty in active mode. Another paper in the power management category presented a 190 nm CMOS, 87% efficiency, 0.75 mm on-chip feed-forward single inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation with 0.5 V startup. Its interesting to see that high voltage technology, techniques and circuits were glaringly missing from the issue that was based on the proceedings of the 2012 Custom Integrated Circuits Conference. There was a preponderance of papers utilizing analog technology ( and RF). Digital type technology was described but not in a large number of papers.