A class F amplifier is highly efficient and uses waveform shaping at the drain of a power device. This shaping takes the form of using ( usually) the second and third harmonic of the waveform to generate a drain to source ( collector to emitter) voltage that is roughly a square wave ( ideally a square wave, but we all know that ideal is a not a word we can use loosely). The drain current is then shaped to be very small when the D/S voltage is high and high when the D/S voltage is low. This causes a non-overlapping condition in operation and ensures a high efficiency. A pre-distortion or pre-conditioning circuit is also required to get the desired linearity. ( This is the subject of a later post). The waveforms below are what we got using Microwave Office as the simulator. The active device was a Cree 40010. It is simply instructive to examine the waveforms in case the reader is starting to design a Class F. The figure below represents the drain source waveform.
The figure above is the D.S current in mA.
The figure below is the simulated power gain and PAE.
We hope these will be of help to aspiring designers of Class F amplifiers. Please visit the Signal Processing Group Inc., website for more information and articles of interest.
FPGA Design and development service
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A wideand RF detector ( 40 Mhz to 3 Ghz) -75 dBm to 5 dBm input
Linear detector performance
A wideband linear RF detector
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Wideband RF detector perforamce , more details
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2 stage 35 dB gain RF amplifier. Front of the module
Full range frequency response
2 stage amplifier deta
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miniature LNA module
Mni LNA performance
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A high frequency divider from 500 Mhz to % Ghz+
The input interface.
The frequency divider has a differential analog interface. The following parameters apply:
The minimum frequency that can be input is 500 Mhz and the maximum frequency is 6.0 Ghz.
The RF input level is 5 dBm to – 5 dBm. For lower frequencies make sure that the slew rate is
greater than 560 V/us. The input is biased by two 500 Ohm resistors connected to a 1.6V DC bias.
Therefore AC coupling is used at the input. These are two 100pF capacitors.
The output interface.
The output is single ended. The output driver is capable of sourcing and sinking 24 mA. The
equivalent output impedance is 50 Ohm. To avoid reflections it is recommended that the divider
work into a 50 Ohm load.
The inputs are applied to the input SMA I/O. The product will work with both a differential input as
well as a single ended input. However, a differential input works best. The division ratio is applied
to the N1 and N2 control inputs as follows:
N2 N1 Division ratio
0 0 8
0 1 16
1 0 32
1 1 64
The logic levels are:
Logic level Voltage
1 1.4V minimum
0 0.6V maximum
The supply voltage interface.
The operating supply voltage is 3.3V typical. The quiescent (DC) operating supply current is 2 mA.
A high frequency divider 500 Mhz to 5 Ghz+
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SPDT DC to 3 Ghz RF switch
DC to 3 Ghz RF SPDT switch
RF Switch typical features
Supply voltage = Vcc = 0/+5 Vdc
Operatng temperature = TA = -50° C to 125 Deg C
Operating impedance = 50 Ohm
Input power for 1 dB
compression ( 5.0V system) = 37 dBm ( f = 0.5 to 3 Ghz)
Input third order Intercept = 64 dBm ( 0 to 5.0V system, f = 0.5 to 3 Ghz)
Operating frequency range = DC to 3 Ghz.
Insertion loss DC to 3 Ghz = 0.8 dB
Isolation DC to 3 Ghz = 14 dB minimum
Return loss DC to 3 Ghz = 20 dB
50% contl to 10/90 %
( ON/OFF) = 120 ns
A single stage RF amplifier as a gain block
A single stage RF amplifier summary specifications
Gain, Operating: 19.5 dB
Operating frequency range: 1.0 – 2700 Mhz
OIP3: (Pout = 19.0 dBm), -8.5 dBm
P1dB: 4.6 dBm
N.F: 4.2 dB
Supply voltage Operating: 3.3 – 5.5 Volts
Price: single unit $7.50, 100 units : $5:50.
Free delivery, shipping lead time 2 days.
30 day return policy, buyer ships.
Supply current Supply = 5.0V, 23.0 mA
Embedded design and development
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