Developing Specifications for an analog/RF/MMIC ASIC

It is true that the quality and success of an analog ASIC generally depends on the specification that is developed for it. A good specification with requirements clearly defined may account for more than 80% of the success, of not only the ASIC device, but also the entire process of development including the business and technical relationship that develops between the customer and analog ASIC vendor.

For it is true that the quality of an analog ASIC is defined by not only how well the device meets the specifications, but also the experience the customer has with the very process of working with the vendor.

It behooves us then, to at least define some basic ground rules for the generation of specifications. It is also true that each analog ASIC will be unique and have its own features, but it is usual for certain items to be included in the specification and follow certain formats.

These issues are explored in this post. We hope this post will be of help to those involved in specifying or implementing an analog ASIC.

This post follows the following outline:

Types of specifications required
Suggested format for the specifications
Challenges in building specifications

1.0 Types of specifications required

In general the specification of an analog chip should be in two parts. The first part is the functional specification and the second part is the test specification.

The functional specification contains a comprehensive description of the chip and all the detailed functionality required by the user. It includes the interaction of the chip with the board ( or substrate ) along with all external components.

The test specification contains the test methods, test options, reliability test options, burn in, thermal operational tests. These numbers and descriptions are usually specified at the I/O of the chip since no other part of the device is available to the outside world.

2.0 Suggested Formats

2.1 Functional Specifications:

2.1.1 The cover page should be the part number of the chip, approvals, revisions and any other high level information.

2.1.2 The next section should provide a clear but brief conceptual level description of the function.

2.1.3 Following the functional description a fairly detailed block diagram with the pin I/O clearly marked should be provided.

2.1.4 A table of pin descriptions should be included which provides clear information on the pin number, the pin name, the pin symbol, whether input or output, and a
succinct description of the function of the pin.

2.1.5 Also included are the absolute maximum ratings for current, voltage, temperature, etc. the chip may be exposed to in extreme cases in a tabular format.

2.1.6 The next section of the specification should clearly describe the principle of operation, timing, flow charts, relevant technical data, operational characteristics etc. in reasonable detail.

2.1.7 Specify the DC operating conditions of the chip including logic levels, power dissipation, supply currents, operating temperature, supply voltages etc. in this section. Minimum, typical and maximum values are preferred along with the symbols of the parameters being specified and the conditions under which the specification has been made.

2.18 Specify the transient operating conditions of the chip, including all delay times, rise and fall times, hold times, setup times, clock frequencies etc. Include timing diagrams if more clarity is required for each parameter. Include symbols for all parameters being specified and the conditions under which the specification is made.

2.19 Specify AC operating conditions. Specify gains, noise levels, input and output impedances, input and output analog voltage and current levels, frequencies, analog accuracies and tolerances etc. Include symbols for all the parameters being specified and the conditions under which the specification is made.

2.110 In the last section include some typical application circuits and/or applications hints that allow the user/designer to understand the operation of the overall system including the role of external components and any test signals. Also include in this section, the suggested board layout for accurate operation of the device. If possible include a specification of the board material or other substrate being recommended for usage.

2.2 Test Specifications:

2.2.1 Cover page is almost identical to that of the functional specifications with all the nomenclature indicating revisions, dates, initiators, approvals and title.

2.2.2 Provide a block diagram of the test architecture showing all external components and any switching relays, matrices of other auxiliary test structures to be used.

2.2.3 Provide a complete pin I/O description. Note that in many cases the test pin I/O list may be more extensive that the functional pin I/O list since there may be test pins included on the device. The package for test may or may not have the same number of pins. Provide a clear description of the pins and their functions.

2.2.4 Provide a complete list of tests to be carried out. Name each test with an appropriate name and number. Link a test description to each test number.

2.2.5 Provide detailed device specific test procedures for each of the tests specified in 2.2.4 above including the role of external supplies and other signals and expected results and tolerances for the results.

3.0 Challenges in building Specifications

It is one thing to say that specifications should be provided for a design to be done accurately and another to actually do it. This is specially the case if the device is a new device with very little functional or test history behind it.

In most cases no one really knows enough about the device to specify it completely. Typically, information that needs to be input into the specifications is non – existent before the device designed. This is the first hurdle or challenge faced by those who would specify the device.

Therefore it is common practice to have a “ preliminary “ specification which is a specification which has a considerable amount of information but also has a lot of “TBD’s” i.e. “ To be determined “ parameters.

The TBD’s can only be replaced by hard data after the chip has been designed and in some cases after the chip has been fabricated and evaluated.

The test specifications are also in a similar position. Since the operating parameters may be unknown the test specification suffers a similar fate with a TBD’s also.

There is a common practice in test specification development where a number of iterations may be performed on the specification. The first test specification may be “ Comprehensive”. This simply means that there is an overkill of tests included in it. These extra tests provide information for the final test specification after the device is designed and fabricated.

As more and more information becomes available the “ Comprehensive “ specification is trimmed downwards with fewer and fewer tests remaining until a final test specification can be approved.

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LNA

SPG designs, develops and delivers custom analog and RF/wireless asics and modules.

FPGA Design and development service

Contact SPG using phone: 602-626-0272 for fast service.

A wideand RF detector ( 40 Mhz to 3 Ghz) -75 dBm to 5 dBm input

A wideband RF detector

A wideband RF detector

Linear detector performance

Linear detector performance curves

A wideband linear RF detector

Price for one unit: $25.00. Lead time for delivery 3 days. 30 Day return policy. Pricing for 100 units or more: $20.00 per unit.  Please contact Signal Processing Group Inc. for details for purchase from Signal Processing Group Inc. Email: spg@signalpro.biz 24/7

Wideband RF detector perforamce , more details

Contact Signal Processing Group Inc.

Please contact Signal Processing Group Inc. on email: spg@signalpro.biz . We will answer within 24 hours.

2 stage 35 dB gain RF amplifier. Front of the module

Full range frequency response

2 stage amplifier deta

Please see details at http://www.signalpro.biz/2rf_amplifier_details.htm    Delivery lead time is 3 days. Return within 30 days for a full refund. Price is $15.00 for one unit and $10.00 per unit in volumes of 100. For higher volumes than 100 please contact Signal Processing group Inc.

miniature LNA module

Mni LNA performance

Delivery lead time is 3 days. Return within 30 days for a full refund. Price is $15.00 for one unit and $12.00 per unit in volumes of 100. For higher volumes than 100 please contact Signal Processing Group Inc. at email: spg@signalpro.biz or call 602-626-0272 for fastest service.

A high frequency divider from 500 Mhz to % Ghz+

The input interface.
The frequency divider has a differential analog interface. The following parameters apply:
The minimum frequency that can be input is 500 Mhz and the maximum frequency is 6.0 Ghz.
The RF input level is 5 dBm to – 5 dBm. For lower frequencies make sure that the slew rate is
greater than 560 V/us. The input is biased by two 500 Ohm resistors connected to a 1.6V DC bias.
Therefore AC coupling is used at the input. These are two 100pF capacitors.
The output interface.
The output is single ended. The output driver is capable of sourcing and sinking 24 mA. The
equivalent output impedance is 50 Ohm. To avoid reflections it is recommended that the divider
work into a 50 Ohm load.
General operation.
The inputs are applied to the input SMA I/O. The product will work with both a differential input as
well as a single ended input. However, a differential input works best. The division ratio is applied
to the N1 and N2 control inputs as follows:
N2 N1 Division ratio
0 0 8
0 1 16
1 0 32
1 1 64
The logic levels are:
Logic level Voltage
1 1.4V minimum
0 0.6V maximum
The supply voltage interface.
The operating supply voltage is 3.3V typical. The quiescent (DC) operating supply current is 2 mA.

A high frequency divider 500 Mhz to 5 Ghz+

Contact Signal Processing Group Inc for details and acquisition

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SPDT DC to 3 Ghz RF switch

DC to 3 Ghz RF SPDT switch

RF Switch typical features

Supply voltage = Vcc = 0/+5 Vdc
Operatng temperature = TA = -50° C to 125 Deg C
Operating impedance = 50 Ohm
Input power for 1 dB
compression ( 5.0V system) = 37 dBm ( f = 0.5 to 3 Ghz)
Input third order Intercept = 64 dBm ( 0 to 5.0V system, f = 0.5 to 3 Ghz)
Operating frequency range = DC to 3 Ghz.
Insertion loss DC to 3 Ghz = 0.8 dB
Isolation DC to 3 Ghz = 14 dB minimum
Return loss DC to 3 Ghz = 20 dB
50% contl to 10/90 %
( ON/OFF) = 120 ns

A single stage RF amplifier as a gain block

A single stage RF amplifier summary specifications

Summary Specifications

Gain,  Operating: 19.5 dB
Operating frequency range: 1.0 – 2700 Mhz
OIP3: (Pout = 19.0 dBm),  -8.5 dBm
P1dB: 4.6 dBm
N.F: 4.2 dB
Supply voltage Operating: 3.3  – 5.5 Volts

Price: single unit $7.50, 100 units : $5:50.

Free delivery, shipping lead time 2 days.

30 day return policy, buyer ships.
Supply current Supply = 5.0V,  23.0 mA

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