About two and half years ago we started a program for the design and development of wireline equalizers, both fixed and adaptive. Our first designs will be going into fabrication this month. This post is an attempt to document some issues and challenges we faced on this project.
1) Data and models of cables: Immediately it was obvious that there is a big hole in the data for cables. Our designs were for 5 Ghz and 1.65 Ghz. We found almost no data on the characteristics of cables for these frequencies. After a little research it turned out that we would have to do our own modeling using a TDR and Simulink/MATLAB and a few home grown tools. This is not an inexpensive activity. The boards required as interfaces to the machine cost about $10k a piece! The TDR is also a very expensive machine. We tried searching the web but found little available data. Manufacturers of the cables do publish data but it turned out that it was the wrong kind of data for our purposes. So cable characteristics are difficult to get.
2) Design tools: The second challenge was, the design tools available for design of ICs are, in our opinion not terribly useful when designing equalizers. Long sequences of really high frequency data are needed to check performance. These types of simulations can really run extremely slow and simulating a complete chip was almost impossible. A combination of SIMULINK and SPICE type simulators ( including Agilent ADS) were used but in our opinion left quite a bit to be desired. Equalizer designers beware!
3) IC process data: The fabrication houses that we selected ( “world class”) provided very good data on their processes. Again this data was good for about 80% of the design but 20% of the design could not be covered by the given data.
4) ESD protection: This is a problem for high frequency equalizer design in particular and in general a good ESD structure is difficult to do. The issue is this: If we use the characterized ESD cells then we have a challenge because of the parasitics. If we make our own ESD cells then we have no characterization data. So I suppose this makes ESD a major challenge in these types of devices. Remembering that the input lines actually come in from outside. ( Existing TVS devices are woefully inadequate for ESD.)
5) Test: The challenge of testing the equalizers looms large of course. A combination of standard lab equipment ( expensive) and custom made equipment is perhaps the best approach. Again the making of the test equipment is a challenge in itself as we found.
6) Demo boards: A real challenge. We had to go through a number of iterations with both PCB vendors and designs. The first PCB we did gave a clear impedance step at 150 Mhz and really caused errors in the measurements. Subsequent designs were great improvements but we still need more improvement and are working on it.
So the design and development of these wireline equalizers is, in our opinion not a “walk in the park” Good luck to all the equalizer designers and many congratulations to the successful ones. You guys have really licked the problems!
FPGA Design and development service
A wideand RF detector ( 40 Mhz to 3 Ghz) -75 dBm to 5 dBm input
A wideband RF detector
Linear detector performance
Linear detector performance curves
Wideband RF detector perforamce , more details
2 stage 35 dB gain RF amplifier. Front of the module
Full range frequency response
miniature LNA module
Mni LNA performance
A high frequency divider 500 Mhz to 5 Ghz+
SPDT DC to 3 Ghz RF switch
A single stage RF amplifier as a gain block
Practical impedance matching
Three useful blocks
