For customers of analog, RF/MMIC ASICS a first pass success is a consummation devoutly to be desired. But what is a “first pass success”? In the strictest sense, a first pass success for an ASIC of any kind means: (i) It works functionally right out of the fab. (ii) It not only works functionally but also meets all the electrical and environmental specifications.
The question then is: Is it possible to develop and fabricate devices which will be first pass successful as per the above definition? I think the answer to this question is quite complicated.
The following set of posts will address this issue.
Anyone who knows about the process of device development, fabrication, testing , packaging and applications knows that each of these steps have their own perils. Therefore to meet the above definition of a first pass success each of these hurdles must be overcome successfully.
Let us first take a look at the device development phase.
During the device development phase, a specification is agreed to, after conceptual deliberations and feasibility studies. The integrity of this specification is very important as this document will be the guide to the rest of the execution. Therefore it is imperative that the specification should be as good as can be with no T.B.D’s. Any T.B.D’s will lead to risk.
After this, the entire chip will be designed from the top down using various design tools appropriate to the type of device. ( MATLAB? ). Once the top level design has been been verified on a functional block basis ( or behavioral basis) the various functional blocks will be converted to circuit schematics.
Each block will then be designed and simulated using industry standard simulation tools ( PSPICE, ADS, CADENCE etc). These simulations will be performed for various ( specified) environmental conditions such as temperature. ( Industrial range, -40 to 85 degrees C or military -55 to 125 degrees C etc). Multiple design reviews with all concerned parties will be held to make sure that these simulations are precise and essential. In this way all the functional blocks will be designed, simulated and finalized.
The next stage of the development will interconnect these functional blocks and attempt to simulate the complete chip over all the required operating conditions. This is a key step in the development and in the pursuit of first pass success. This is explained below.
Note that the simulations of the chip are done using electrical and geometrical models provided by the fabrication facility and the packaging facility. It is absolutely essential that a fab and a packager be picked that provides a complete set of these models and certifies that these models are up to date and accurate. The reason is simple. If the models are not accurate, the simulations will also be inaccurate and the device will fail to operate as required and first pass success will be thwarted!
Assume for the moment that the models provided are accurate. The next question is about the simulation tools being used and the nature of the device being simulated. The simulator tool can simulate very complicated circuits but it has some real problems when a certain set of conditions of simulation are met. For example convergence of DC and transient solutions can be a very real hazard. DC convergence problems can occur with the existence of very high impedance nodes or branches in the circuit. Transient non convergence can occur when there are very long and very short time constants involved in the circuit. Analog and digital circuits in the same circuit can be a big problem because they are very difficult to simulate.
There are analog simulators and digital simulators but a true mixed signal simulator is not really available. Analog simulators simulate time point ( or frequency point) by point and thus generate a very large number of data points .
Digital simuators generate a true or false data set. Therefore if there is significant digital content in the circuit the data generated by the analog simulator will be very large and swamp the computer memory. A digital simulator will be incapable of simulating the small analog steps required for precise analog simulation. In addition the time for simulation will be so long as to be really not practical. In general a fairly small mixed signal device can play havoc with the simulations! This is not a practical way of simulating this class of circuits. No one really knows currently of a practical way of simulating these type of circuits.
Having understood this, it is now possible to point to risk number one for the failure of the device upon first pass. If the complete chip cannot be simulated a 100% then the probability that the chip will be a first pass success will be lower than 100%.
How can one estimate the probability of success quantitatively?
The difference between 100% simulation of the entire chip and the actual depth of simulation will be the risk that the chip will not meet the specifications on the first pass depending on the circuit simulation issues alone. Therefore to avoid this risk, the chip must be 100% simulated. If it cannot, then one has to assume the risk mentioned above.
Following the simulation of the chip, layout will be done ( or even before the chip simulation is complete). The layout is the second most critical part of the process which will determine first pass success. There is no correct or incorrect way of doing layout in general, except insofar as all the foundry layout rules are obeyed and the layout is LVS compliant. ( LVS = Layout versus schematic verification).
However, for analog and RFIC/MMIC designs layout becomes a very critical activity, since shape, placement and interconnect type of the layout elements becomes important to performance of the chip. Matching of active and passive devices is dependent on how close these devices are on the layout. They need to be in the same orientation. For temperature critical elements, the devices ( resistors, capacitors, active devices) may not only have to obey shape and orientation rules but also lie on isothermals on the chip surface. Fringe capacitors can lead to unintended coupling of signals. For a high gain, wideband amplifier, input and output traces placed close together can lead to parasitic oscillation! Ground shielding must be used whenever there is a danger of unintended coupling for reasons of size or electrical performance.
Matching of devices is also important. Common centroid layout ( layout of sections of a passive device or a number of matched active devices around a common pivotal point) has to be used. For reduction of offset the usual differential pair may have to be split into a quad and cross-connected.
If the device is a radhard device a number of other techniques have to used, specially for CMOS type devices where threshold shifts with radiation will almost certainly kill the performance/device.
There are a multitude of layout techniques, beyond the scope of this post which have to be learned through experience. The point however, is this. Even if all these techniques are used the layout of the device is more susceptible to errors which lead to chip failure ( and thereby miss the first pass criterion) than schematic errors.
In spite of this a number of devices can indeed be first pass successful. However, in the author’s experience these are fairly simple devices where the level of criticality is low. In such devices first pass success can be expected and many times, found.
Thus, there is a finite risk of failure due to layout issues.
The next step in the chip path is the fabrication.
The fabrication of the device is carried out in the foundry selected. Hopefully, the foundry will be a good one, providing precise models and design rules/process rules which will be certified.
The foundry will run its own DRC ( design rules checks) on the chip database sent to them for fabrication. If the DRC toolset at the foundry and that at the customer are correlated then no DRC errors will be found at this stage. However, the usual case is, that there will be some errors found at this juncture. These errors will have to be corrected ( or waived) by the customer. In the author’s opinion waiving errors is not a safe option. All DRC errors should be corrected before fabrication is started. If not, this will lead to another risk that the chip may fail first pass success.
As the fabrication proceeds the customer will be given access to the WIP ( Work in Progress) database and when the fabrication ends the customer will receive the finished wafers and the process control module test results. The wafer test results must be scrutinized for compliance with upper and lower level limits of all parameters.
Again sometimes the fabricator cannot meet the process limits and may ask for a waiver. This should be considered very seriously as any parameters out of limits can cause a failure of the device.
The bottom line is this. There should be no DRC errors in the final DRC run by the fabricator and no waivers asked for before/after the processing, if we are to eliminate the risk of the fabrication causing a chip failure .
Finally if all goes well the wafers should be available for a probe test using a test program ( or a manual probe test) which will be the first evaluation of the device ( before packaging). If the simulations are accurate, the layout is accurate and the fabrication is done correctly, the probe test should yield first pass functional devices.
However, we are not there yet. The device must be packaged ( usually) and the package test must yield good devices. As is well known package parasitics can have severe effects on the device performance, specially if it is a high performance device. This problem can be avoided of course, by making sure precise package parasitics are available when the device is in the simulation stage. If this is not done, then there is a finite probability of the device failing the packaged test.
Finally if the device does pass the packaged test, it must be inserted into the board or the system it was designed to operate in. Here the device may be subjected to various forms of stress such as EMI, RFI, thermal. mechanical, noise, etc, etc. In order for the device to pass this test, it should have been designed to operate in the environment it is in now. This is why a great deal of attention must be paid to the deliberations and assessments during the conceptual stage of development. In the author’s opinion the road to first pass success really starts at that point.
Significant attention during the conceptual phase is a good approach, which leads to a positive result at the end of the entire process. If this is not done then there is a finite probability that the device will fail at this late stage which is a really catastrophic event by any standards.
As can be seen, to ensure a first pass success a great many factors must be taken into account and due diligence paid to them. In spite of this approximately 5%-10% of devices fail to be first pass functional ( studies have shown) for one reason or the other and may have to be re-iterated with a reduced set of masks.. This factor should always be taken into consideration when planning a new high performance analog or RF ASIC or MMIC.
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A wideand RF detector ( 40 Mhz to 3 Ghz) -75 dBm to 5 dBm input
Linear detector performance
A wideband linear RF detector
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Wideband RF detector perforamce , more details
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2 stage 35 dB gain RF amplifier. Front of the module
Full range frequency response
2 stage amplifier deta
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miniature LNA module
Mni LNA performance
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A high frequency divider from 500 Mhz to % Ghz+
The input interface.
The frequency divider has a differential analog interface. The following parameters apply:
The minimum frequency that can be input is 500 Mhz and the maximum frequency is 6.0 Ghz.
The RF input level is 5 dBm to – 5 dBm. For lower frequencies make sure that the slew rate is
greater than 560 V/us. The input is biased by two 500 Ohm resistors connected to a 1.6V DC bias.
Therefore AC coupling is used at the input. These are two 100pF capacitors.
The output interface.
The output is single ended. The output driver is capable of sourcing and sinking 24 mA. The
equivalent output impedance is 50 Ohm. To avoid reflections it is recommended that the divider
work into a 50 Ohm load.
The inputs are applied to the input SMA I/O. The product will work with both a differential input as
well as a single ended input. However, a differential input works best. The division ratio is applied
to the N1 and N2 control inputs as follows:
N2 N1 Division ratio
0 0 8
0 1 16
1 0 32
1 1 64
The logic levels are:
Logic level Voltage
1 1.4V minimum
0 0.6V maximum
The supply voltage interface.
The operating supply voltage is 3.3V typical. The quiescent (DC) operating supply current is 2 mA.
A high frequency divider 500 Mhz to 5 Ghz+
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SPDT DC to 3 Ghz RF switch
DC to 3 Ghz RF SPDT switch
RF Switch typical features
Supply voltage = Vcc = 0/+5 Vdc
Operatng temperature = TA = -50° C to 125 Deg C
Operating impedance = 50 Ohm
Input power for 1 dB
compression ( 5.0V system) = 37 dBm ( f = 0.5 to 3 Ghz)
Input third order Intercept = 64 dBm ( 0 to 5.0V system, f = 0.5 to 3 Ghz)
Operating frequency range = DC to 3 Ghz.
Insertion loss DC to 3 Ghz = 0.8 dB
Isolation DC to 3 Ghz = 14 dB minimum
Return loss DC to 3 Ghz = 20 dB
50% contl to 10/90 %
( ON/OFF) = 120 ns
A single stage RF amplifier as a gain block
A single stage RF amplifier summary specifications
Gain, Operating: 19.5 dB
Operating frequency range: 1.0 – 2700 Mhz
OIP3: (Pout = 19.0 dBm), -8.5 dBm
P1dB: 4.6 dBm
N.F: 4.2 dB
Supply voltage Operating: 3.3 – 5.5 Volts
Price: single unit $7.50, 100 units : $5:50.
Free delivery, shipping lead time 2 days.
30 day return policy, buyer ships.
Supply current Supply = 5.0V, 23.0 mA