In an earlier post ( http://www.signalpro.biz/wordpress/phase-locked-loop-pll-acquisition-behavior-mathematical-expressions/) an approximate expression for the acquisition time of a PLL was tabulated with conditions for its use. The text describing the conditions was left out. The following are the conditions for the use of that expression.
FPGA Design and development service
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A wideand RF detector ( 40 Mhz to 3 Ghz) -75 dBm to 5 dBm input
Linear detector performance
A wideband linear RF detector
Price for one unit: $25.00. Lead time for delivery 3 days. 30 Day return policy. Pricing for 100 units or more: $20.00 per unit. Please contact Signal Processing Group Inc. for details for purchase from Signal Processing Group Inc. Email: firstname.lastname@example.org 24/7
Wideband RF detector perforamce , more details
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2 stage 35 dB gain RF amplifier. Front of the module
Full range frequency response
2 stage amplifier deta
Please see details at http://www.signalpro.biz/2rf_amplifier_details.htm Delivery lead time is 3 days. Return within 30 days for a full refund. Price is $15.00 for one unit and $10.00 per unit in volumes of 100. For higher volumes than 100 please contact Signal Processing group Inc.
miniature LNA module
Mni LNA performance
Delivery lead time is 3 days. Return within 30 days for a full refund. Price is $15.00 for one unit and $12.00 per unit in volumes of 100. For higher volumes than 100 please contact Signal Processing Group Inc. at email: firstname.lastname@example.org or call 602-626-0272 for fastest service.
A high frequency divider from 500 Mhz to % Ghz+
The input interface.
The frequency divider has a differential analog interface. The following parameters apply:
The minimum frequency that can be input is 500 Mhz and the maximum frequency is 6.0 Ghz.
The RF input level is 5 dBm to – 5 dBm. For lower frequencies make sure that the slew rate is
greater than 560 V/us. The input is biased by two 500 Ohm resistors connected to a 1.6V DC bias.
Therefore AC coupling is used at the input. These are two 100pF capacitors.
The output interface.
The output is single ended. The output driver is capable of sourcing and sinking 24 mA. The
equivalent output impedance is 50 Ohm. To avoid reflections it is recommended that the divider
work into a 50 Ohm load.
The inputs are applied to the input SMA I/O. The product will work with both a differential input as
well as a single ended input. However, a differential input works best. The division ratio is applied
to the N1 and N2 control inputs as follows:
N2 N1 Division ratio
0 0 8
0 1 16
1 0 32
1 1 64
The logic levels are:
Logic level Voltage
1 1.4V minimum
0 0.6V maximum
The supply voltage interface.
The operating supply voltage is 3.3V typical. The quiescent (DC) operating supply current is 2 mA.
A high frequency divider 500 Mhz to 5 Ghz+
Contact Signal Processing Group Inc for details and acquisition
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SPDT DC to 3 Ghz RF switch
DC to 3 Ghz RF SPDT switch
RF Switch typical features
Supply voltage = Vcc = 0/+5 Vdc
Operatng temperature = TA = -50° C to 125 Deg C
Operating impedance = 50 Ohm
Input power for 1 dB
compression ( 5.0V system) = 37 dBm ( f = 0.5 to 3 Ghz)
Input third order Intercept = 64 dBm ( 0 to 5.0V system, f = 0.5 to 3 Ghz)
Operating frequency range = DC to 3 Ghz.
Insertion loss DC to 3 Ghz = 0.8 dB
Isolation DC to 3 Ghz = 14 dB minimum
Return loss DC to 3 Ghz = 20 dB
50% contl to 10/90 %
( ON/OFF) = 120 ns
A single stage RF amplifier as a gain block
A single stage RF amplifier summary specifications
Gain, Operating: 19.5 dB
Operating frequency range: 1.0 – 2700 Mhz
OIP3: (Pout = 19.0 dBm), -8.5 dBm
P1dB: 4.6 dBm
N.F: 4.2 dB
Supply voltage Operating: 3.3 – 5.5 Volts
Price: single unit $7.50, 100 units : $5:50.
Free delivery, shipping lead time 2 days.
30 day return policy, buyer ships.
Supply current Supply = 5.0V, 23.0 mA
Embedded design and development
Signal Processing Group Inc. is offering embedded design and development using Microchip processors. Please contact us on firstname.lastname@example.org for more information