This is a short post that follows on to the last post about QPSK modulation techniques using a I/Q modulator. The description was based on idealized operation of the modulator in an effort to explain the operation. The real world effects were not explored. The fact is that I/Q modulators have at least two impairments that affect the accuracy of the transmitted signal. In order to explain this, note that the phase shifts in QPSK are also realized through the gain of the I/Q channels. Thus if there is an imbalance in the gain of the two channels then an error in the transmitted constellation will occur. If either the I or Q channel is imbalanced with respect to the other, the constellation will change from a square shape to a rectangular shape. If there are also phase errors then the constellation will change to a parallelogram and so on. These are the two most important impairments in the I/Q modulation scheme. Another impairment in the overall transmitter is the non-linearity of the final power amplifier. This will affect the constellation too. The white additive noise in the transmitter and the receiver will cause the received constellation to be spread out in the phase/gain space. Under worst case conditions the constellation may cease to exist and extreme loss of bit error rate will result. However, as far as impairments in the I/Q modulator are concerned, it may be a relief to know that modern day I/Q modulators have very low gain and phase errors. For example a well known device has a gain error of 0.12 dB and a phase error of 0.05 degree. In addition trimming of these errors can also be achieved using digital to analog converters and non volatile memory storage. The errors are trimmed out in the factory before final delivery.
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The input interface.
The frequency divider has a differential analog interface. The following parameters apply:
The minimum frequency that can be input is 500 Mhz and the maximum frequency is 6.0 Ghz.
The RF input level is 5 dBm to – 5 dBm. For lower frequencies make sure that the slew rate is
greater than 560 V/us. The input is biased by two 500 Ohm resistors connected to a 1.6V DC bias.
Therefore AC coupling is used at the input. These are two 100pF capacitors.
The output interface.
The output is single ended. The output driver is capable of sourcing and sinking 24 mA. The
equivalent output impedance is 50 Ohm. To avoid reflections it is recommended that the divider
work into a 50 Ohm load.
General operation.
The inputs are applied to the input SMA I/O. The product will work with both a differential input as
well as a single ended input. However, a differential input works best. The division ratio is applied
to the N1 and N2 control inputs as follows:
N2 N1 Division ratio
0 0 8
0 1 16
1 0 32
1 1 64
The logic levels are:
Logic level Voltage
1 1.4V minimum
0 0.6V maximum
The supply voltage interface.
The operating supply voltage is 3.3V typical. The quiescent (DC) operating supply current is 2 mA.
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RF Switch typical features
Supply voltage = Vcc = 0/+5 Vdc
Operatng temperature = TA = -50° C to 125 Deg C
Operating impedance = 50 Ohm
Input power for 1 dB
compression ( 5.0V system) = 37 dBm ( f = 0.5 to 3 Ghz)
Input third order Intercept = 64 dBm ( 0 to 5.0V system, f = 0.5 to 3 Ghz)
Operating frequency range = DC to 3 Ghz.
Insertion loss DC to 3 Ghz = 0.8 dB
Isolation DC to 3 Ghz = 14 dB minimum
Return loss DC to 3 Ghz = 20 dB
50% contl to 10/90 %
( ON/OFF) = 120 ns
Summary Specifications
Gain, Operating: 19.5 dB
Operating frequency range: 1.0 – 2700 Mhz
OIP3: (Pout = 19.0 dBm), -8.5 dBm
P1dB: 4.6 dBm
N.F: 4.2 dB
Supply voltage Operating: 3.3 – 5.5 Volts
Price: single unit $7.50, 100 units : $5:50.
Free delivery, shipping lead time 2 days.
30 day return policy, buyer ships.
Supply current Supply = 5.0V, 23.0 mA
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