A common circuit used in most wireless receivers is the RSSI circuit or block. It simply measures or provides an indication of the signal strength being received. It is usually implemented within the receiver chip. The circuitry used for the RSSI appears to be simple but there are a number of issues that must be borne in mind. To begin with, a RSSI circuit can be implemented using the concept of log amplifiers. A really good source of information on these is the Analog Devices website. It may take a bit of searching to find the right article but it is worth it.Also a tutorial article has been already published in these blog posts which may be of some use. However, through experience it has been found ( at SPG) that even if we follow prior art on RSSI design it still takes some doing. Here are a few tips if one is thinking of doing a rssi circuit. ( Of course higher frequencies complicate things even more). (1) Must understand the techniques intuitively. (2) Select a process that can meet the ft/IKF/Hfe/CBC requirements easily. (3)Simulations will take a long time so must be prepared for long simulation times. (4) Bond pad and package parasitics will play a significant role in the performance. So the more accurate these are the better. If package parasitic information is not available then it must be generated ( which is a project in its own right). For more information please access the RSSI design paper in the SPG website located at http://www.signalpro.biz, under engineering pages or contact SPG directly using the contact details provided.

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Delivery lead time is 3 days. Return within 30 days for a full refund. Price is $15.00 for one unit and $12.00 per unit in volumes of 100. For higher volumes than 100 please contact Signal Processing Group Inc. at email: spg@signalpro.biz or call 602-626-0272 for fastest service.
The input interface.
The frequency divider has a differential analog interface. The following parameters apply:
The minimum frequency that can be input is 500 Mhz and the maximum frequency is 6.0 Ghz.
The RF input level is 5 dBm to – 5 dBm. For lower frequencies make sure that the slew rate is
greater than 560 V/us. The input is biased by two 500 Ohm resistors connected to a 1.6V DC bias.
Therefore AC coupling is used at the input. These are two 100pF capacitors.
The output interface.
The output is single ended. The output driver is capable of sourcing and sinking 24 mA. The
equivalent output impedance is 50 Ohm. To avoid reflections it is recommended that the divider
work into a 50 Ohm load.
General operation.
The inputs are applied to the input SMA I/O. The product will work with both a differential input as
well as a single ended input. However, a differential input works best. The division ratio is applied
to the N1 and N2 control inputs as follows:
N2 N1 Division ratio
0 0 8
0 1 16
1 0 32
1 1 64
The logic levels are:
Logic level Voltage
1 1.4V minimum
0 0.6V maximum
The supply voltage interface.
The operating supply voltage is 3.3V typical. The quiescent (DC) operating supply current is 2 mA.
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RF Switch typical features
Supply voltage = Vcc = 0/+5 Vdc
Operatng temperature = TA = -50° C to 125 Deg C
Operating impedance = 50 Ohm
Input power for 1 dB
compression ( 5.0V system) = 37 dBm ( f = 0.5 to 3 Ghz)
Input third order Intercept = 64 dBm ( 0 to 5.0V system, f = 0.5 to 3 Ghz)
Operating frequency range = DC to 3 Ghz.
Insertion loss DC to 3 Ghz = 0.8 dB
Isolation DC to 3 Ghz = 14 dB minimum
Return loss DC to 3 Ghz = 20 dB
50% contl to 10/90 %
( ON/OFF) = 120 ns
Summary Specifications
Gain, Operating: 19.5 dB
Operating frequency range: 1.0 – 2700 Mhz
OIP3: (Pout = 19.0 dBm), -8.5 dBm
P1dB: 4.6 dBm
N.F: 4.2 dB
Supply voltage Operating: 3.3 – 5.5 Volts
Price: single unit $7.50, 100 units : $5:50.
Free delivery, shipping lead time 2 days.
30 day return policy, buyer ships.
Supply current Supply = 5.0V, 23.0 mA
Signal Processing Group Inc. is offering embedded design and development using Microchip processors. Please contact us on spg@signalpro.biz for more information