More and more DSP ( digital signal processing) techniques are being used in most complex circuit designs including IC design. In general dsp requires the use of binary numbers. After all dsp is akin to a set of computations yielding a result which may or may not be converted into an analog signal. Both ways. At the input using an A/D and at the output using a D/A. In fact this is the way many recent designs in wireless are being implemented. The number system most often used is the 2-s complement number system. To refresh our memories, a 2-s complement number is formed by taking the binary representation of a decimal number, inverting the bits and then adding a “1” to it. This generates the 2-s complement. A wealth of articles exist on this in the literature and the web. The nice thing about the 2-s complement number is that addition and subtraction become very easy. An example is a dual modulus frequency divider. In this circuit we have two counters that start with a loaded number, an initial seed, and then this number is counted down. When the loaded number goes to zero a reset occurs. This is almost the very basic operation required in a dual modulus frequency divider. Note how easy the countdown becomes when implemented with 2-s complement numbers. Have the initial storage in a set of FFs, at each clock invert the contents of the FFs, use a simple adder, add 1 and at the falling edge of the clock recapture the results back into the storage FFs. Each time the clock occurs the FFs count down by ‘1’. Please visit the Signal Processing Group Inc., website located at http:/www.signalpro.biz for more information on our unique services, technology and technical articles. Contact us on this or other blog posts or articles as needed.

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**The input interface.**

The frequency divider has a differential analog interface. The following parameters apply:

The minimum frequency that can be input is 500 Mhz and the maximum frequency is 6.0 Ghz.

The RF input level is 5 dBm to – 5 dBm. For lower frequencies make sure that the slew rate is

greater than 560 V/us. The input is biased by two 500 Ohm resistors connected to a 1.6V DC bias.

Therefore AC coupling is used at the input. These are two 100pF capacitors.

**The output interface.**

The output is single ended. The output driver is capable of sourcing and sinking 24 mA. The

equivalent output impedance is 50 Ohm. To avoid reflections it is recommended that the divider

work into a 50 Ohm load.

**General operation.**

The inputs are applied to the input SMA I/O. The product will work with both a differential input as

well as a single ended input. However, a differential input works best. The division ratio is applied

to the N1 and N2 control inputs as follows:

N2 N1 Division ratio

0 0 8

0 1 16

1 0 32

1 1 64

The logic levels are:

Logic level Voltage

1 1.4V minimum

0 0.6V maximum

The supply voltage interface.

The operating supply voltage is 3.3V typical. The quiescent (DC) operating supply current is 2 mA.

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**RF Switch typical features**

Supply voltage = Vcc = 0/+5 Vdc

Operatng temperature = TA = -50° C to 125 Deg C

Operating impedance = 50 Ohm

Input power for 1 dB

compression ( 5.0V system) = 37 dBm ( f = 0.5 to 3 Ghz)

Input third order Intercept = 64 dBm ( 0 to 5.0V system, f = 0.5 to 3 Ghz)

Operating frequency range = DC to 3 Ghz.

Insertion loss DC to 3 Ghz = 0.8 dB

Isolation DC to 3 Ghz = 14 dB minimum

Return loss DC to 3 Ghz = 20 dB

50% contl to 10/90 %

( ON/OFF) = 120 ns

Summary Specifications

Gain, Operating: 19.5 dB

Operating frequency range: 1.0 – 2700 Mhz

OIP3: (Pout = 19.0 dBm), -8.5 dBm

P1dB: 4.6 dBm

N.F: 4.2 dB

Supply voltage Operating: 3.3 – 5.5 Volts

Price: single unit $7.50, 100 units : $5:50.

Free delivery, shipping lead time 2 days.

30 day return policy, buyer ships.

Supply current Supply = 5.0V, 23.0 mA

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