The 2012 IEEE Custom Integrated Circuits Conference summary

Looking at the issue of the IEEE Journal of Solid State Circuits, after the 2012 Custom IC conference, with a critical eye for analog and RF content, the following interesting articles were found. A 3W class-D amplifier with improved linearity was described that reduces external filtering required for EMI protection by controlling the slew rate of the driver amplifier and digital modulation to spread the PWM common mode signal to place a null at the victim channel. The 110 nm CMOS design achieves SNR of 95 dB at 85% efficiency. A second article describes a 2.3 mW 10-bit 170 MS/s ADC in 65 nm CMOS using a two-step binary-search assisted time-interleaved SAR architecture. The third article , presents a continuous-time sigma-delta ADC with a switched-capacitor return-to-zero DAC that helps to reduce sensitivity to clock jitter and improves linearity. The prototype ADC was designed in a 180 nm process. It achieves an SNDR of 82.3 dB for a 2 MHz bandwidth while consuming 16.5 mW and reduces clock jitter sensitivity by 28 dB. An interesting article describes comprehensive design considerations for interleaved ADCs and proposes a background timing mismatch calibration technique to reduce the image to 75 dB for input frequencies more than 500 MHz. Another article presents a 40 nm 2.1 GS/s 2x time-interleaved pipeline ADC tthat uses a digital MDAC equalization techniques using FIR filters. The 12-bit design achieves SNDR of 52 dB while consuming 240 mW. In terms of topics in RF design some interesting articles described various RF techniques such as: A digital PLL that uses a coarse/fine TDC. The fine TDC is implemented using stochastic techniques to achieve an overall TDC resolution of 4 ps. The concept is demonstrated in a 130 nm 1.99–2.5 GHz PLL with 213 fs rms integrated jitter. The next paper in this series describes dynamic latches, where the regenerative cross-coupled pair is removed for maximum speed, demonstrated in prototypes of divide-by-4 circuits in 32 nm CMOS operated between 14 GHz and 70 GHz. A switched-triple-shielded transformer technique to realize a wideband CMOS VCO that can tune from 57.5 GHz to 90.1 GHz was also presented. An interesting paper provided reviews of techniques for improved harmonic reject mixers using clock gating that allow better than 52 dB rejection for 3rd/5th/7th LO harmonics without any calibration. This should be of interest to front end designers. There were papers on wireline topics as well. A paper presented a reference-less CDR for SONET transceivers that uses an algorithmic frequency acquisition without using a training sequence. The concept was demonstrated on a 65 nm transceiver that achieves 400s acquisition time and a jitter tolerance of 0.5 UI for 10 mVppd( differential) input sensitivity. Another paper on the wireline topics describes a 20 mW 6b 1.6 GS/s ADC with embedded partial equalization using a 1-tap DFE for serial receivers. The prototype receiver is demonstrated at 1.6 GS/s over 46-inch FR4 link with 14 dB loss while achieving a 0.2 UI timing margin. The next paper presented a 10 Gb/s 2-tap reconfigurable pre-emphasis transmitter that consumes 10 mW in a 65 nm LP CMOS. Power management was not ignored and papers described advances in power management techniques especially for SoC applications. An interesting paper for an adaptive all-digital ripple mitigation technique for fully integrated capacitive DC-DC converters was presented. Coarse ripple control was achieved by varying the size of the bucket capacitance, and fine control by time modulation of the charge/discharge charge transfer capacitors. The 130 nm design presented achieved 3x ripple reduction, 70% efficiency, and 24.5 mW/mm maximum power density. A power management unit was presented with a reconfigurable switched-capacitor converter in 65 nm CMOS to reduce the energy cost with sleep-to-active and active-to-sleep transitions by 64%. This energy reduction comes at small area overhead (lower than 1%) and no penalty in active mode. Another paper in the power management category presented a 190 nm CMOS, 87% efficiency, 0.75 mm on-chip feed-forward single inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation with 0.5 V startup. Its interesting to see that high voltage technology, techniques and circuits were glaringly missing from the issue that was based on the proceedings of the 2012 Custom Integrated Circuits Conference. There was a preponderance of papers utilizing analog technology ( and RF). Digital type technology was described but not in a large number of papers.

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A wideand RF detector ( 40 Mhz to 3 Ghz) -75 dBm to 5 dBm input

A wideband RF detector

A wideband RF detector

Linear detector performance

Linear detector performance curves

A wideband linear RF detector

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Wideband RF detector perforamce , more details

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2 stage 35 dB gain RF amplifier. Front of the module

Full range frequency response

2 stage amplifier deta

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miniature LNA module

Mni LNA performance

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A high frequency divider from 500 Mhz to % Ghz+

The input interface.
The frequency divider has a differential analog interface. The following parameters apply:
The minimum frequency that can be input is 500 Mhz and the maximum frequency is 6.0 Ghz.
The RF input level is 5 dBm to – 5 dBm. For lower frequencies make sure that the slew rate is
greater than 560 V/us. The input is biased by two 500 Ohm resistors connected to a 1.6V DC bias.
Therefore AC coupling is used at the input. These are two 100pF capacitors.
The output interface.
The output is single ended. The output driver is capable of sourcing and sinking 24 mA. The
equivalent output impedance is 50 Ohm. To avoid reflections it is recommended that the divider
work into a 50 Ohm load.
General operation.
The inputs are applied to the input SMA I/O. The product will work with both a differential input as
well as a single ended input. However, a differential input works best. The division ratio is applied
to the N1 and N2 control inputs as follows:
N2 N1 Division ratio
0 0 8
0 1 16
1 0 32
1 1 64
The logic levels are:
Logic level Voltage
1 1.4V minimum
0 0.6V maximum
The supply voltage interface.
The operating supply voltage is 3.3V typical. The quiescent (DC) operating supply current is 2 mA.

A high frequency divider 500 Mhz to 5 Ghz+

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SPDT DC to 3 Ghz RF switch

DC to 3 Ghz RF SPDT switch

RF Switch typical features

Supply voltage = Vcc = 0/+5 Vdc
Operatng temperature = TA = -50° C to 125 Deg C
Operating impedance = 50 Ohm
Input power for 1 dB
compression ( 5.0V system) = 37 dBm ( f = 0.5 to 3 Ghz)
Input third order Intercept = 64 dBm ( 0 to 5.0V system, f = 0.5 to 3 Ghz)
Operating frequency range = DC to 3 Ghz.
Insertion loss DC to 3 Ghz = 0.8 dB
Isolation DC to 3 Ghz = 14 dB minimum
Return loss DC to 3 Ghz = 20 dB
50% contl to 10/90 %
( ON/OFF) = 120 ns

A single stage RF amplifier as a gain block

A single stage RF amplifier summary specifications

Summary Specifications

Gain,  Operating: 19.5 dB
Operating frequency range: 1.0 – 2700 Mhz
OIP3: (Pout = 19.0 dBm),  -8.5 dBm
P1dB: 4.6 dBm
N.F: 4.2 dB
Supply voltage Operating: 3.3  – 5.5 Volts

Price: single unit $7.50, 100 units : $5:50.

Free delivery, shipping lead time 2 days.

30 day return policy, buyer ships.
Supply current Supply = 5.0V,  23.0 mA

Embedded design and development

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Practical impedance matching

Three useful blocks

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