VCO behavioral model using PSPICE ABM ( analog behavioral models)

A VCO is fairly difficult to simulate. When designing a PLL ( phase locked loop) it helps to use a behavioral model of a VCO to begin the design. This is because a behavioral model runs fast and is cheaper in simulation time and engineering time. There are a number of ways to do this. However, a popular way is to use PSPICE ABM modeling to implement the VCO behavioral model. In a recent post Signal Processing Group Inc.’s technical team has released a white paper that describes this. The paper also includes simulation results and the run file used. Interested parties may access this paper from the complementary items link on the SPG website.

Phase locked loop acquisition time

In an earlier post ( an approximate expression for the acquisition time of a PLL was tabulated with conditions for its use. The text describing the conditions was left out. The following are the conditions for the use of that expression.


Phase Locked Loop ( PLL) acquisition behavior mathematical expressions

A PLL has multiple phases of operation. One of the early phases is the acquisition of a signal and lock-in to its VCO frequency. This behavior is complex and hard to specify exactly using analytical expressions. However, a number of approximate expressions have been derived that can form the starting point of numerical, iterative analysis. Failing this, it becomes very difficult to even start the design of a PLL. In a recent paper released by Signal Processing Group Inc., these fundamental expressions are examined and presented for interested readers. Please visit the SPG website and use the “complementary” link to access this paper.