Digital PLL design analysis

  1. The clock distribution within a customer’s digital chip relies strongly on de – skewing the regional clock signals typically using an all digital PLL. We propose an approach for this ADPLL with respect to a CMOS 0.18um process. A compromise is required so that size, power and jitter may be minimized.
  • Specifications: From an analysis of the clock distribution network we have formulated the specifications for the ADPLL frequency synthesizer.
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