Charge pump PLL design analysis for a 0.18um CMOS process

A charge pump PLL is a popular way to design a PLL. It is a good idea to analyze its requirements and relate the design to those parameters even before the functional blocks are designed. This provides the design engineer a pathway to complete the design from behavioral modeling to a final semiconductor layout to be fabricated. The higher level analysis can be done very quickly and lays bare the techniques, risks, timelines etc. for the design. A recent whitepaper by Signal Processing Group Inc. presents these assessments. The article can be found under the complementary menu in the SPG website. Please visit the SPG website for this and other articles of interest.

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