Analog and mixed signal design: A reduced power capacitive load CMOS clock driver

When designing clock drivers for capacitive loads ( or indeed for any load), using a CMOS inverter type driver, the power dissipation can be large if precautions are not taken to attenuate the direct current that flows from the P or N channel output transistors, when, for a fraction of the drive cycle both the transistors may be momentarily ON.

A simple way to alleviate this problem is to use a non – overlapping clock driver. Such a driver is presented on our website at’s corner.
A simple and useful circuit.