Differential and Integral non – linearity in a DAC

Differential and Integral non – linearity specifications are important specifications for a DAC.

Differential non-linearity in a DAC is a specification that describes the difference between two analog values corresponding to adjacent input digital values.The accuracy of a digital to analog converter is determined by this specification. Any two adjacent digital codes should correspond to output analog voltages that are exactly one Least Significant Bit (LSB) apart. Differential non-linearity measures the worst case difference from the ideal 1 LSB step. A DAC with a 1.5 LSB output change for a 1 LSB digital code change has a 0.5 LSB differential non-linearity.

Integral non-linearity describes the maximum deviation between the ideal output of a DAC and the actual output level after offset and gain errors have been taken into account. It is an important specification for measuring error in a digital-to-analog converter.The transfer function of a DAC should be a straight line. INL measurement depends on the ideal line selected. Lines typically used are the best fit line, the line that minimizes the INL result and the endpoint line that passes through the points on the transfer function corresponding to the lowest and highest input code. The INL is the maximum difference between the ideal line and the actual transfer function.

We design and deliver analog and RF/wireless ASICs and modules using state of the art semiconductor, PCB and assembly technologies. Please contact us at spg@signalpro.biz for a quote and a proposal.

Bluetooth Low Energy ( LE) radio performance summary.

Bluetooth LE is a very useful standard that uses low power radios to communicate with devices over short distances. It has many attractive features not the least being very low power consumption. Here is a brief list of the features of the Bluetooth LE radios. The modulation used is GMSK ( Gaussian Frequency Shift Keying) and the frequency band is the 2,4 Ghz ISM band.A ‘0’ bit uses a negative frequency deviation while a ‘1’ bit uses a positive frequency deviation. 40 channels can be used. The center frequency of the lowest channel is 2402 Mhz while the center frequency of the highest channel is 2480 Mhz. To calculate the center frequencies of the channels use: fcenter(i) = 2402 + 2i  Mhz. i varies from 0 to 39.The center frequency tolerance is + or – 150Khz. The center frequency cannot drift by more than 50 Khz during a packet transmission. The transmit power is a maximum of +10 dBm and the minimum is -20dBm.The receiver sensitivity is – 70 dBm The sensitivity threshold is set at 0,1% BER. Some numbers for operating range can be calculated using a LINK BUDGET with a theoretical isotropic antenna and by ignoring any transmit or receive losses. For the minimum transmit power the range is approximately 2.5 meters. For the maximum transmit power the approximate range is 80 meters. Of course this depends on the receiver sensitivity. These numbers are for the minimum receiver sensitivity of -70 dBm.

We design and deliver analog and RF/wireless ASICs and modules using state of the art semiconductor, PCB and assembly technologies. Please contact us at spg@signalpro.biz for a quote and a proposal.

QPSK modulation analysis and explanations using semi-graphical techniques

QPSK is a modulation technique for digital communications. It provides a way to send more information ( or information bits) in the channel then many other techniques. It uses a form of phase modulation to send “symbols” consistng of di-bits ( two bits for each symbol). A recent short paper released by Signal Processing Group Inc., describes the basis of the QPSK techniques using very little mathermatics and more graphics to clearly illustrate the operation. The paper may be accessed from the SPG website located at http://www.signalpro.biz using the “Free reports …” menu item. .

We design and deliver analog and RF/wireless ASICs and modules using state of the art semiconductor, PCB and assembly technologies. Please contact us at spg@signalpro.biz for a quote and a proposal.

Bond wire fusing current calculator

A previous post concerning the fusing current of a bond wire established an expression for the fusing of a bond wire under pulsed current conditions. Two new posts extend this information further by: (1) Introducing a calculator to find this current under various conditions and , (2) a supplementary note to establish the equivalency of the units used in the calculation. This introductory note can be found here. The actual calculator can be accessed by visiting our website located at http://www.signalpro.biz and accessing the free reports section. The calculator may be used or downloaded from that section.

We design and deliver analog and RF/wireless ASICs and modules using state of the art semiconductor, PCB and assembly technologies. Please contact us at spg@signalpro.biz for a quote and a proposal.

 

Bond wire inductance – resistance calculator

The inductance and resistance of the bondwire can play a significant role in the performance of a high performance integrated circuit. This being the case it behooves the design engineer to include these parasitic bond wire components in the final simulations of the chip. Although the most accurate values of these parameters can only be available from the assembly companies for the IC, analytical models have been developed by standards bodies like the JEDEC. A calculator based on these models has been developed and is available here. A very brief paper is also available on these models and has been described elsewhere in these posts. For more information on this please visit the Signal Processing Group Inc. website located at http://www.signalpro.biz.

We design and deliver analog and RF/wireless ASICs and modules using state of the art semiconductor, PCB and assembly technologies. Please contact us at spg@signalpro.biz for a quote and a proposal.

Bond wire inductance, mutual inductance and other information

Bond wires can have a significant effect on the performance of Integrated circuits. High frequency and high power circuits are more susceptible but almost all circuits can be affected. It is therefore prudent to look at the models of bond wires and include these effects in the top level chip design simulations. (The effect of the complete package is also important and can be modeled using “Touchstone” files. See the description and use of these files elsewhere in this blog and the SPG website at http://www.signalpro.biz) . A recent brief paper on bond wire parameter models may be found on the SPG website at http://www.signalpro.biz under the “Download …” menu item.

Signal Processing Group Inc, designs, develops and delivers analog and RF/wireless asics and modules, using state of the art semiconductor, pcb and assembly technologies. Please contact us at spg@signalpro.biz and visit our website at http://www.signalpro.biz.

 

Skin effect: What is it and why is it important

The skin effect in power transmission occurs with AC signals. The outer surface – the “skin” of the wire/trace is used more than the inner part of the conductor to carry current. This causes an increase in the effective resistance of the wire.The depth into the conductor at which the charge carrier current density falls to l/e, or 37% of its value along the surface, is known as the skin depth and is a function of the frequency, the permeability and conductivity of the medium.Skin depth is inversely proportional to frequency. Skin depth also varies with the type of material.The skin effect causes high frequency ( HF) signals to be concentrated near the surface, the “skin”, of a conductor. For HF signals braided copper wires are used, which have a larger combined surface.At very high frequencies, all the current goes through the “skin”. The fundamental formula that is used to calculate skin depth is:

The skin depth in conductors carrying H.F. currentsHere :

ω = angular frequency (rads/sec)
μ = permeability of the medium(Henries/meter)
σ = conductivity of the trace/wire ( Siemens/meter)
Data on material properties can be found at the two links below:
http://en.wikipedia.org/wiki/Permeability_(electromagnetism)
http://en.wikipedia.org/wiki/Electrical_conductivity

A script is available to calculate skin effect and can be found here.

We design and deliver analog and RF/wireless ASICs and modules using state of the art semiconductor, PCB and assembly technologies. Please contact us at spg@signalpro.biz for a quote and a proposal.

 

 

FR4 speed limitations for high speed clocks

FR4 is a very popular material for PCBs. It is low cost and robust and is used for a multitude of applications. However, it does have some speed limitations when it comes to its use as a substrate material for high speed digital circuits ( as well as analog circuits. The analog and RF circuit limitations are presented in another post). An estimate for the upper limit of operation of logic clocks is presented in a very brief note in the Signal Processing Group Inc., website located at http://www.signalpro.biz. The note can be found in the “Engineer’s Corner”.