Ground loops in analog and wireless design

Ground loops are parasitic paths in a PCB or an IC that can cause a number of bad effects. These are caused primarily by bad layout, circuit design or interconnections either accidentally or because of lack of experience. In order to avoid ground loops one has to understand what they are. A very brief description is given in a recent article by the techteam at Signal Processing Group Inc., and is available for review at their “engineering pages” in the website located at

Ultra low power ASIC design

Power has become a limiting factor in many applications. Specially in portable products, wireless applications and temperature limited products and systems. Therefore it is useful to investigate and develop really low power, “ultra” low power devices ( Integrated circuits and modules) that can be used to build more complex systems. techniques such as low voltage devices, sub-threshold CMOS circuits, energy harvesting etc. all play a part in the design of such devices. It is a fascinating area of design. Over the past few years the techteam at Signal Processing Group Inc, has been involved in the design of low power circuits for use in RFID and 1.2V battery powered systems. Some of this work is available for discussion. For details or for help in the design of these type of devices please contact SPG at

Silicon nitride, the “other” dielectric material

Silicon nitride is used in integrated circuits wherever a high dielectric material is required. We are most used to silicon dioxide as the dielectric used in IC fabrication. Silicon nitride has some properies that makes it a better dielectric sometimes. One of the chief ones is its use in the fabrication of higher value on chip capacitance. Its dielectric constant is approximately twice that of silicon dioxide. So a sandwich capacitor made using nitride will be twice as large in the same area as it would be if oxide was used. Common properties of nitride are listed in a table located at

Accuracy of schematics of older analog ICs

It is an interesting fact that if datasheets of older ( 70’s – 80’s)devices are examined then then it will be found that the datasheet usually includes a detailed device level datasheet. This is more of a case with analog chips. Large analog device manufacturers have been more than generous in providing these with the datasheet as a guide for designers. The issue is though if the schematic is compared to the actual layout ( for example by taking a photo of the die) then many, many discrepancies will be found. This can lead to some very interesting errors in the design of the product with really no help from manufacturer as to why an effect may be seen to happen. In the case of the uA741 for example there are at least two or three different datasheet schematics available. Neither of them are accurate. So user beware. For more information on this topic please contact Signal Processing Group Inc, via their website at

A case study of a successful analog and mixed signal ASIC project

Although much has been written about the ASIC business model. It is still useful to study a real ASIC project in terms of the interactions of supplier and customer, timelines and the typical path from concept to a successful implementation, that allowed the customer to actually put his product into the market. ASIC development can be a very exciting and pleasant activity if certain methodology is followed by both parties, the supplier and customer. A case study that was released recently by SPG allows potential participants to get a feel, at a high level, of a successful ASIC project. The document may be accessed from the SPG website located at It can be found under the menu item ” Engineer’s Corner”

Multipath wireless solutions: The RAKE receiver

Multipath in wireless systems is what happens when a transmitted signal travels along multiple paths ( e.g. as a result of reflections from surfaces). At the receiver these received signals can add or subtract depending on the amplitude and phase of the signals causing what is known as frequency selective fading. Another name for multipath interference. Obviously this is a real problem for cellular systems and many different types of solutions have been proposed and are being used. One of these solutions is the so-called RAKE receiver. The RAKE receiver has a number of “sub-receivers” called fingers, each assigned to a different multipath component. Each finger independently receives a single multipath signal. Subsequently, the contribution of all fingers are combined in order to make the most use of the different transmission characteristics of each transmission path. The important parameters that need to be estimated as accurately as possible are, the time of arrival of each finger signal, its amplitude and phase. Knowing these, the signals are combined in what is known as a maximal ratio combiner or a MRC. In this combiner each individual finger signal is weighted by the complex valued channel gain. The effect of this weighting is to compensate for the phase shifts in the channel and the change in amplitude. As this is done successfully significant improvement in signal reception is obtained. For details on a RAKE receiver design please contact Signal Processing Group Inc., through the website located at

A simple, silicon proven BiCMOS volage reference

Voltage references are ubiquitous components of analog design. The specifications of references vary depending on the application they are used in, from ultra accurate to simple. In most cases a simple voltage reference that is guaranteed to start up and provide a relatively accurate and stable reference voltage over temperature and power supply voltage is all that is necessary. Trimming is another task that can become complicated for references. However a simple voltage reference application may not even require that. In a recent free report released by the Techteam at Signal Processing Group Inc., a simple silicon proven voltage reference is presented It can be used as is, or if necessary can form a core cell for a more involved design. The report can be accessed at This design is available for implementation in a FASTCHIP project if needed.