Analog and mixed signal design: Multi-die designs in a package.

As the levels of integration of integrated devices increase, engineers are looking for newer and unique ways to increase the levels of integration at low risk and cost. If the subsystem design to be integrated has widely varying performance, i.e high and low voltages, high and low currents, high and low frequencies etc. then it is not possible to use a single technology to integrate the device. In this case a multidie approach in a package is the best approach. In this technique chips with varying performance are put inside a package and interconnected. The die are fully isolated from each other so the interaction between them is assumed to be minimal ( or designed to be minimal). So an overall subsystem can be integrated inside a package. The advantages here are that a long and costly process of custom chip design can be avoided and varying specifications implemented. In recent years SPG has been doing this type of integration with success. Anyone with interest in this technique is invited to contact SPG through the website located at

Quick turn analog ICs with low risk : The SPG Fastchip technique

It is not unusual that the trio of risk factors: cost, timeline and performance are the inhibitors of analog and mixed ASIC usage. Techniques that can lower these risks can and should be used. The lowest order of risk reduction techniques is breadboarding. Using discrete devices to verify a circuit. However, there are a number drawbacks to this. First of all, a breadboard has higher parasitics ( capacitance, inductance and resistance) and when the design is transferred to an ASIC, performance may not match that obtained on a breadboard. Secondly it is not always that one can get discrete devices which are appropriate for the ASIC design. There are other factors of minor importance that also affect the mapping of a breadboard design to an ASIC. What is needed is a method to cheaply and quickly check out either part or all of a envisaged ASIC cheaply. The SPG Fastchip technique is one approach that is available from Signal Processing Group Inc. Its description may be found under “Engineer’s corner” in our website at:

Reverse engineering obsolete devices

In our work on resurrecting really old and obsolete devices using bipolar technology, some designed using rubylith techniques, we found an interesting evolutionary trend from the oldest to the older. The layout techniques and the basic designs were dictated by the availablity of or non-availability of CAD tools. The earliest designs tend to have the very simplest layouts for the individual devices such as: simple epi-tub, base and emitter rectangular diffusions. Large contact areas of every shape and description and very broad isolation and device to device spacings starting at almost 10 mils and coming down to about a mil for the older devices. Devices are layed out almost as one would layout a PCB using discrete devices. Active devices occupy their own tubs, resistors occupy their tubs and there is a general absence of capacitors. For the relatively newer obsolete devices the layout style changes to active devices, resistors sometimes occupying a single tub with very unique shapes and geometries. As the the CAD tools become better, circular geometries become more and more prevalent and we see lateral pnps and smaller npns with circular emitters. On chip capacitors make their appearance using the emitter diffusion, oxide /nitride and metal sandwiches. The line widths shrink down to sub mil sizes and device densities per chip increase. Interestingly bondpad sizes seem to be consistent for a long period of time ( around 100 um X 100 um). Scribe lines appear to also hold on to widths. ( Around 100 to 150 um wide). All in all the art of reverse engineering these devices, including the electrical characteristics as deduced from the layout and ancient specifications form a most interesting activity for those interested in the art. Interested parties may contact SPG for reverse engineering of obsolete parts via our website at

Learning from failures

This year SPG will be over 24 years old. We have had a long history of projects, most of which were great successes. A few of them spectacular failures. After much soul searching we decided to publish what we think were some outstanding reasons for the failures. As is understandable and usual there were shortcomings and challenges on both sides. SPG and the customer. This post tries to list these and should be read with respect to one of the earliest posts about first pass success, already published in this blog. The reason for this baring of skeletons is to help establish a better and better methodology for success and to avoid mistakes of the past. It may be slightly controversial but its veracity is unquestionable.

Project # 1.0 ( Non – chip project)
1.0 Communication problems. Customer and SPG not communicating comfortably and well.
2.0 No statement of work. No plan. No list of things to do and a timeline associated with it.
3.0 No clear guidance from the customer.
4.0 Bad, bad, bad documentation from the customer. Bits and pieces strung together in random order. Failure of SPG to not accept this.
5.0 Micro – managing by the customer instead of managing.
6.0 Too much anxiety on the customer’s part about the project.
7.0 No specification.

Project #2
1.0 Change of specifications and mission creep.
2.0 Failure to do full chip simulations.
3.0 Initial time estimates were off. Too aggressive a schedule.
4.0 Delay in implementation. Faults on both sides.

Project #3
1.0 Change of specifications. Mission creep.
2.0 Customer pushing to get the database out too quickly before checking got done.
3.0 Severe micro-management by customer..
4.0 Did not correct DRC or LVS problems completely because of 2.0
5.0 Lack of pcb expertise on the customers part.
6.0 Would not let us do the reference pcb design and initial test.

Project #4
1.0 Lack of right design tools and training to use them
2.0 Lack of good communication and comfortable give and take between the two parties.
3.0 Lack of appropriate effort on the project.

Project #5

1.0 Lack of the right process technology.
2.0 Used a process that did not have comfortable performance margins.
3.0 Circuit failure under stress conditions.